Bruno Glecer

Xilinx provides a tool called XilinxVirtualCable (XVC) that allows the developer to debug a Zynq7000 FPGA SoC though an ethernet connection. This software runs on the PS of the Zynq, it acts as an interface between Vivado communicating through LAN, and the Debug Bridge instantiated in the PL communicating through AXI (Mapped memory from the POV of the PS).

In PetaLinux, this mapped memory is provided by the device /dev/uio0. But in general, this device has to be implemented manually in case of using a different OS. Adding this in requires implementing the device in the Linux Device Tree for the given platform, this can be tircky to do depending on the system. To circumvent this, it's possible to rewrite the XVC server to instead use /dev/mem to access the Debug Bridge.

This are the only changes one needs to make to XVC:

...
#define MAP_SIZE 0x10000
#define MAP_ADDR 0x43C00000
...
char *d = "mem";
...
volatile jtag_t* ptr = (volatile jtag_t*) mmap(NULL, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd_uio, MAP_ADDR);
...

The modified file can be found in the following repository:

IMPORTANT: When running the server, make sure the bitstream is loaded and the Debug Bridge is connectes via AXI to the PS, otherwise the OS will crash immediatly, requiring a hard reset